There has been proposed a conventional technology for reducing wiring design worker-hours of a multilayer printed wiring board on which arranged are surface-mounted components, which are packaged using methods such as BGA (Ball Grid Array), QFP (Quad Flat Package), and SOP (Small Outline Package) (hereinafter, these components are referred to as “BGA”, “QFP”, and “SFP” as needed) (e.g., see Japanese Laid-open Patent Publication No. 2006-11684).
For example, when a designer carries out, on a multilayer printed wiring board, wiring design for connecting a BGA located on the surface of a board and a bypass capacitor located on the back surface of the board, the designer checks whether the board permits the use of Chip On Hole (COH). When the board permits the use of COH, the designer makes a via that leads from the surface of the board to the bypass capacitor on the back surface of the board and then carries out leading wiring from the BGA on the surface of the board to the via, so that the BGA and the bypass capacitor are connected through a via.
When it turns out that the board does not permit the use of COH as a result of checking whether the board in use permits the use of COH, the designer makes vias, leading to an inner layer of the board, near the BGA and the bypass capacitor, and then carries out leading wiring from the BGA to the bypass capacitor, so that the BGA and the bypass capacitor are connected through the vias.
There is a problem with the conventional technology in that it requires a huge amount of operation time. A designer carries out leading wiring for connecting the surface-mounted component with the bypass capacitor by forming a via by trial and error, e.g., checks whether using COH on the board is allowed, which results in a large amount of operation time.
Further, when the designer carries out different leading wiring for connecting the surface-mounted component with a signal pin after preferentially carrying out leading wiring for connecting the surface-mounted component with the bypass capacitor by trial and error, a situation sometimes arises where the designer cannot carry out the different leading wiring for connecting the surface-mounted component with the signal pin. In case of such a situation, the designer needs to start over the operation by correcting the wired parts and carrying out leading wiring without overlooking any wiring. This start-over is a primary factor in the increase in the operation time.
With the further advancement in signal speed transmitting among semiconductor integrated circuits, not only a bypass capacitor but also a damping resistor may be located on the back surface of the board. Therefore, it may be preferable that COH be used, if possible, so that the wiring space of the back surface of the board can be effectively used.
The present invention is made in order to solve the above-mentioned problems with the conventional technology. An object of the present invention is to provide a leading wiring method, a leading wiring program, and a leading wiring apparatus that prevent the start-over of the operation and shorten the operation time of leading wiring considerably.